数字/混合信号设计验证工程师 | Design Verification Engineer (Digital/Mixed Signal)

岗位职责：

You will be part of a team that performs verification planning and AMS simulation on full custom ASICs designs

You will implement an improve functional verification of mixed-signal ASICs

Develop test plans, testbenches, and verification methodologies to verify the microarchitecture and design

You will perform failure analysis and resolution, coverage analysis and population

In depth knowledge of digital/mixed-signal modelling

Develop directed/constraint-random test generation, gate-simulations

Performing regression debug support, and other flow/infrastructure development

任职要求：

| Experience in Design Verification (DV) of Complex IP, CPU Systems and/or SoC

| Experienced in latest DV methodologies: Formal Verification, System Verilog and UVM, Assembly/C-based Verification, Mixed-signal IP Verification, AMS …

| Proven ability to develop and deploy new DV methodologies

| Experienced in developing a DV plan based on Functional Specification, build the necessary test bench/infrastructure, develop tests and verify design

| Strong debugging skills and familiar with using industry standard simulation (e.g.: VCS) and debug tools

| Strong scripting skills

学历要求：

|电子工程、微电子相关专业本科以上学历

工作地点：北京